Multiplier-less and compact FPGA implementation of Mihalas-Niebur neuron

被引：0

作者：

Kongpoon, Metha ^{[1
]}

Leelavattananon, Kritsapon ^{[1
]}

机构：

[1] King Mongkuts Inst Technol Ladkrabang, Fac Engn, Dept Elect Engn, Bangkok, Thailand

来源：

2019 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS 2019) | 2019年

关键词：

Mihalas-Niebur neuron; FPGA; multiplier-less neuron; compact implementation;

D O I：

10.1109/apccas47518.2019.8953116

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The modified Mihalas-Niebur neuron model suitable for a compact digital implementation is presented. Based on the modified model, a multiplier-less and compact Mihalas-Niebur neuron that uses word-length optimization and bitwise shifting operators for the multiplication was designed and implemented on an FPGA. The simulation results show that the proposed neuron successfully produces all 20 prominent spiking patterns with a few FPGA resources used.

引用

页码：321 / 324

页数：4

共 36 条

[31] FPGA Implementation of Multiplier Less Matched Filters to Transmit Video Signals Over Satellites
Srividya, P.
Nataraj, K. R.
Rekha, K. R.
2014 INTERNATIONAL CONFERENCE ON COMMUNICATIONS AND SIGNAL PROCESSING (ICCSP), 2014,
[32] Design and multiplier-less implementation of a class of two-channel PR FIR filterbanks and wavelets with low system delay
Mao, JS
Chan, SC
Liu, W
Ho, KL
IEEE TRANSACTIONS ON SIGNAL PROCESSING, 2000, 48 (12) : 3379 - 3394
[33] 4-bit CNN Quantization Method With Compact LUT-Based Multiplier Implementation on FPGA
Zhao, Bingrui
Wang, Yaonan
Zhang, Hui
Zhang, Jinzhou
Chen, Yurong
Yang, Yimin
IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, 2023, 72 : 1 - 10
[34] FPGA implementation of parallel pipelined multiplier less FFT architecture based system-on-chip design targetting multimedia applications
Sreejaa, B. S.
Jayanthy, T.
Logashanmugam, E.
2007 INTERNATIONAL CONFERENCE OF SIGNAL PROCESSING, COMMUNICATIONS AND NETWORKING, VOLS 1 AND 2, 2006, : 592 - +
[35] FPGA Implementation of a modified FitzHugh-Nagumo neuron based Causal Neural Network for Compact Internal Representation of Dynamic Environments
Salas-Paracuellos, L.
Alba, Luis
Villacorta-Atienza, Jose A.
Makarov, Valeri A.
BIOELECTRONICS, BIOMEDICAL, AND BIOINSPIRED SYSTEMS V AND NANOTECHNOLOGY V, 2011, 8068
[36] Secure and compact implementation of optimized Montgomery multiplier based elliptic curve cryptography on FPGA with road vehicular traffic collecting protocol for VANET application
Baskar, S.
Dhulipala, V. R. Sarma
INTERNATIONAL JOURNAL OF HEAVY VEHICLE SYSTEMS, 2018, 25 (3-4) : 485 - 497

← 1 2 3 4 →