Multiplier-less and compact FPGA implementation of Mihalas-Niebur neuron

被引：0

作者：

Kongpoon, Metha ^{[1
]}

Leelavattananon, Kritsapon ^{[1
]}

机构：

[1] King Mongkuts Inst Technol Ladkrabang, Fac Engn, Dept Elect Engn, Bangkok, Thailand

来源：

2019 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS 2019) | 2019年

关键词：

Mihalas-Niebur neuron; FPGA; multiplier-less neuron; compact implementation;

D O I：

10.1109/apccas47518.2019.8953116

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The modified Mihalas-Niebur neuron model suitable for a compact digital implementation is presented. Based on the modified model, a multiplier-less and compact Mihalas-Niebur neuron that uses word-length optimization and bitwise shifting operators for the multiplication was designed and implemented on an FPGA. The simulation results show that the proposed neuron successfully produces all 20 prominent spiking patterns with a few FPGA resources used.

引用

页码：321 / 324

页数：4

共 36 条

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