共 50 条
- [41] Mining Task Precedence Graphs from Real-Time Embedded System Traces 24TH IEEE REAL-TIME AND EMBEDDED TECHNOLOGY AND APPLICATIONS SYMPOSIUM (RTAS 2018), 2018, : 251 - 260
- [42] Fault Tolerant Heterogeneous Scheduling for Precedence Constrained Task Graphs Using Simulated Annealing 2013 8TH INTERNATIONAL CONFERENCE ON COMPUTER ENGINEERING & SYSTEMS (ICCES), 2013, : 307 - 312
- [47] Platform designer: An approach for modeling multiprocessor platforms based on SystemC Design Automation for Embedded Systems, 2005, 10 : 253 - 283
- [48] High level modeling and simulation of a VDSL modem in SystemC 2.0 - IPsim 3RD IEEE INTERNATIONAL WORKSHOP ON SYSTEM-ON-CHIP FOR REAL-TIME APPLICATIONS, PROCEEDINGS, 2003, : 175 - 180
- [49] SystemC NoC Simulation as the Alternative to the HDL and High-level Modeling 2016 18TH CONFERENCE OF OPEN INNOVATIONS ASSOCIATION AND SEMINAR ON INFORMATION SECURITY AND PROTECTION OF INFORMATION TECHNOLOGY (FRUCT-ISPIT), 2016, : 285 - 290
- [50] A SystemC-based Framework for Modeling and Simulation of Networked Embedded Systems 2008 FORUM ON SPECIFICATION, VERIFICATION AND DESIGN LANGUAGES, 2008, : 73 - 78