A pipelined SoPC architecture for Data Link Layer Protocol processing

被引：0
|
作者：
Sezer, S [1 ]
Toal, C [1 ]
Yu, X [1 ]
机构：
[1] Queens Univ Belfast, Sch Elect & Elect Engn, Belfast BT9 5AH, Antrim, North Ireland
来源：
IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS | 2003年
关键词：
D O I：
10.1109/SOC.2003.1241519
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper presents the architecture and implementation of a 2.5Gbps Programmable Data Link Layer Protocol Processor on a Virtex II FPGA. A 32-bit wide pipelined processor circuit is implemented for Point-to-Point protocol processing (PPP) and a Leon processor core is embedded for higher layer PPP control protocol processing. An AMBA bus interface is used to interlink the Leon processor to the hardware frame processing unit and presents a standard interface allowing easy retargeting to other processor platforms. Complex memory control is implemented to enable the microprocessor to handle control packets arriving at 2.5 Gbps. The high-level system breakdown is described and Virtex II synthesis results presented.
引用
收藏
页码：277 / 278
页数：2
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