Cooperative communication based barrier synchronization in on-chip mesh architectures

被引:3
|
作者
Chen, Xiaowen [1 ,2 ]
Lu, Zhonghai [2 ]
Jantsch, Axel [2 ]
Chen, Shuming [1 ]
Liu, Hai [1 ]
机构
[1] Natl Univ Def Technol, Changsha 410073, Hunan, Peoples R China
[2] KTH Royal Inst Technol, S-16440 Stockholm, Sweden
来源
IEICE ELECTRONICS EXPRESS | 2011年 / 8卷 / 22期
基金
中国国家自然科学基金;
关键词
cooperative communication; barrier synchronization;
D O I
10.1587/elex.8.1856
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
We propose cooperative communication as a means to enable efficient and scalable barrier synchronization on mesh-based many-core architectures. Our approach is different from but orthogonal to conventional algorithm-based optimizations. It relies on collaborating routers to provide efficient gather and multicast communication. In conjunction with a master-slave algorithm, it exploits the mesh regularity to achieve efficiency. The gather and multicast functions have been implemented in our router. Synthesis results suggest marginal area overhead. With synthetic and benchmark experiments, we show that our approach significantly reduces synchronization completion time and increases speedup.
引用
收藏
页码:1856 / 1862
页数:7
相关论文
共 50 条
  • [21] Dynamically Reconfigurable On-Chip Communication Architectures for Multi Use-Case Chip Multiprocessor Applications
    Pasricha, Sudeep
    Dutt, Nikil
    Kurdahi, Fadi J.
    PROCEEDINGS OF THE ASP-DAC 2009: ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 2009, 2009, : 25 - 30
  • [22] Evaluation and run-time optimization of on-chip communication structures in reconfigurable architectures
    Murgan, T
    Petrov, M
    Ortiz, AG
    Ludewig, R
    Zipf, P
    Hollstein, T
    Glesner, M
    Oelkrug, B
    Brakensiek, J
    FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS, PROCEEDINGS, 2003, 2778 : 1111 - 1114
  • [23] Enabling Reliable High Throughput On-Chip Wireless Communication for Many Core Architectures
    Gade, Sri Harsha
    Sinha, Mitali
    Rout, Sidhartha Sankar
    Deb, Sujay
    2018 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI), 2018, : 591 - 596
  • [24] Full System Exploration of On-Chip Wireless Communication on Many-Core Architectures
    Medina, Rafael
    Kein, Joshua
    Qureshi, Yasir
    Zapater, Marina
    Ansaloni, Giovanni
    Atienza, David
    2022 IEEE 13TH LATIN AMERICAN SYMPOSIUM ON CIRCUITS AND SYSTEMS (LASCAS), 2022, : 200 - 203
  • [25] Modeling on-chip communication
    Seceleanu, T
    Plosila, J
    INTERNATIONAL SYMPOSIUM ON SYSTEM-ON-CHIP, PROCEEDINGS, 2003, : 89 - 92
  • [26] Robust on-chip communication
    Bose, P
    IEEE MICRO, 2006, 26 (03) : 5 - 5
  • [27] Simulation-based approach for evaluating On-Chip Interconnect architectures
    Suboh, Suboh
    Bakhouya, Mohamed
    Lopez-Buedo, Sergio
    El-Ghazawi, Tarek
    2008 4TH SOUTHERN CONFERENCE ON PROGRAMMABLE LOGIC, PROCEEDINGS, 2008, : 75 - 80
  • [28] On-chip stochastic communication
    Dumitras, T
    Marculescu, R
    EMBEDDED SOFTWARE FOR SOC, 2003, : 373 - 386
  • [29] On-chip stochastic communication
    Dumitras, T
    Marculescu, R
    DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, PROCEEDINGS, 2003, : 790 - 795
  • [30] Methodology for adapting on-chip interconnect architectures
    Suboh, Suboh
    Narayana, Vikram
    Bakhouya, Mohamed
    Gaber, Jaafar
    El-Ghazawi, Tarek
    IET COMPUTERS AND DIGITAL TECHNIQUES, 2014, 8 (03): : 109 - 117