Modeling of Graphene for Interconnect Applications

We modeled the electrostatic doping in multilayer graphene interconnects by self-consistently solving Poisson's equation and we computed the resistivity per layer by accounting for acoustic and optical phonon scattering. For the analysis, we used two different doping concentrations, representative for graphene on top of hexagonal Boron Nitride and SiO2 substrates. Finally, we benchmarked graphene against Cu interconnects at 10 nm half-pitch in terms of resistance, capacitance, RC delay and circuit delay. Our results show that at least ten layers of graphene are needed in order to achieve lower resistance than Cu. On the other hand, due to the reduced graphene thickness, only four graphene layers are required to outperform Cu in terms of RC delay, because of the lower capacitance. About circuit delay, depending on the assumed contact resistance value, five to ten graphene layers are needed for 3.2 mu m long wires to outperform Cu at the 5 nm logic technology node.