On-chip ESD protection design for integrated circuits: an overview for IC designers

被引：32

作者：

Wang, AZ ^{[1
]}

Feng, HG ^{[1
]}

Gong, K ^{[1
]}

Zhan, RY ^{[1
]}

Stine, J ^{[1
]}

机构：

[1] IIT, Dept Elect & Comp Engn, Integrated Elect Lab, Chicago, IL 60616 USA

来源：

MICROELECTRONICS JOURNAL | 2001年 / 32卷 / 09期

关键词：

electrostatic discharging; integrated circuits; ESD; HDM; MM; CDM;

D O I：

10.1016/S0026-2692(01)00060-X

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This tutorial paper reviews the state of knowledge of on-chip ESD (electrostatic discharging) protection circuit design for integrated circuits. The discussion covers critical issues in ESD protection design, i.e. ESD test models, ESD failure mechanisms, ESD protection structures, ESD device modeling, ESD simulation, ESD layout issues, and ESD-to-circuit interactions, etc. This review serves to provide practical IC designers with a thorough and heady reference in dealing with complex ESD protection design for integrated circuits. (C) 2001 Published by Elsevier Science Ltd.

引用

页码：733 / 747

页数：15

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