A 3.5 GHz High-efficiency CMOS RF Power Amplifier with Adaptive Bias

This paper proposes a high-efficiency 3.5 GHz CMOS power amplifier that uses an improved linearizer as an adaptive bias control circuit. The proposed circuit is simulated by TSMC 0.18 mu m RF CMOS process. At the 1-dB compression point (P1dB), the power amplifier exhibits 25.5 dBm of output power with a high power-added-efficiency (PAE) of 39% and sufficient gain (25.5 dB) at a supply voltage of 3.3 V. At the output power 6-dB back-off from P1dB, the PAE remains at 15%. The proposed structure improves PAE by 5%similar to 6% more than the resistor bias.