Debug of the CELL processor: Moving the lab into silicon

被引：0

作者：

Riley, Mack ^{[1
]}

Chelstrom, Nathan ^{[1
]}

Genden, Mike ^{[1
]}

Sawamura, Shoji ^{[2
]}

机构：

[1] IBM Syst & Technol Grp, Austin, TX USA

[2] Toshiba Co Ltd, Semicond Co, Kawasaki, Kanagawa 210, Japan

来源：

2006 IEEE INTERNATIONAL TEST CONFERENCE, VOLS 1 AND 2 | 2006年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

With 234 million transistors, making up 9 processing units and 3 asynchronous clock domains in a high speed design, the CELL processor clearly presents a challenge to debug work required during lab bring-up and test bring-up. Traditional multiprocessing systems reap the benefit of standard system level debug practices, but as the system has moved into the silicon so must the access during bring-up. This paper explains some of the innovative debug features included in the CELL processor design that were critical for efficient bring-up in a limited access environment.

引用

页码：735 / +

页数：2

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