FMAP: A technology mapping algorithm for FPGA with MUX-LUT mixed architecture

被引：0
|
作者：
Wen, YJ [1 ]
Tong, JR [1 ]
Chiang, C [1 ]
机构：
[1] Fudan Univ, Shanghai, Peoples R China
来源：
2003 5TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS | 2003年
关键词：
D O I：
10.1109/ICASIC.2003.1277334
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Because of its advantages of the short design turnaround time and the convenience and low cost in integrated circuit prototyping and verification. the field programmable gate array (FPGA) has been widely utilized in many fields of electronic design. In this paper, a technology mapping algorithm for FPGA with MUX-LUT mixed architecture is presented. This algorithm, FMAP, is used in a design-aided software system for FPGA, which is developed specifically for ail FPGA chip. FDP, with MUX-LUT mixed architecture. The bench marking result of technology mapping for FDP by FMAP is compared to the result of the Xilinx series by their design system. The result is also presented in this paper.
引用
收藏
页码：812 / 815
页数：4
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