High Throughput Four-Parallel RS Decoder Architecture for 60GHz mmWAVE WPAN Systems

被引：0

作者：

Choi, Chang-Seok ^{[1
]}

Lee, Hanho ^{[1
]}

机构：

[1] Inha Univ, Inchon, South Korea

来源：

2010 DIGEST OF TECHNICAL PAPERS INTERNATIONAL CONFERENCE ON CONSUMER ELECTRONICS ICCE | 2010年

关键词：

OPTICAL COMMUNICATIONS;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a high-throughput low-complexity four-parallel Reed-Solomon (RS) decoder for mmWAVE WPAN systems. Four-parallel processing is used to achieve 6-Gbps data throughput and low hardware complexity. The proposed four-parallel RS decoder has been implemented 90nm CMOS technology optimized for a 1.2V supply voltage. The implementation result shows that the proposed RS decoder can operates at a clock frequency of 400MHz and has a data throughput 12.8-Gbps. The proposed four-parallel RS decoder architecture has high data processing rate and low hardware complexity, and also can be adapted in the FEC devices for mmWave WPAN systems with a data rate of 6-Gbps and beyond

引用

页数：2