Comparison of Level Shifter Architectures: Application to I/O cell

被引：0

作者：

Petrica, Radu-Valentin ^{[1
,2
]}

Dobre, Mihaela-Daniela ^{[1
,2
]}

Coll, Philippe ^{[1
]}

Draghici, Florin ^{[2
]}

Brezeanu, Gheorghe ^{[2
]}

机构：

[1] Microchip Technol Inc, Chandler, AZ USA

[2] Univ Politehn, Bucharest, Romania

来源：

CAS 2018 PROCEEDINGS: 2018 INTERNATIONAL SEMICONDUCTOR CONFERENCE | 2018年

关键词：

native devices; level shifter; I/O strucutre; low voltage;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Novel low-voltage and high-speed level shifter topologies will be presented. The level shifters circuits were designed in 40 nm technology using 1.2V devices and zero-VT transistors. These techniques will provide functionality near the threshold region. The simulated results were compared with a reference architecture. The resulted level shifters will be integrated in an already tested I/O structure. The results were analyzed in terms of electrical performance and silicon area.

引用

页码：209 / 212

页数：4

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