A DC-50 GHz SPDT Switch with Maximum Insertion Loss of 1.9 dB in a Commercial 0.13-μm SOI Technology

被引：0

作者：

Yu, Bo ^{[1
]}

Ma, Kaixue ^{[2
]}

Meng, Fanyi ^{[1
]}

Yang, Wanlan ^{[1
]}

Yeo, Kiat Seng ^{[3
]}

Zhang, Shaoqiang ^{[4
]}

Purakh, Raj Verma ^{[4
]}

机构：

[1] Nanyang Technol Univ, Sch EEE, Singapore, Singapore

[2] UESTC, Sch Phys Elect, Chengdu, Peoples R China

[3] Singapore Univ Technol & Design, Singapore, Singapore

[4] GLOBALFOUNDRIES, Technol Dev, Singapore, Singapore

来源：

2015 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC) | 2015年

关键词：

SPDT; switch; ultra wideband; NMOS transistor; channel length; gate bias effect; SOI process;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, a low insertion loss, high isolation, ultra wideband (DC to 50 GHz) single-pole double-throw (SPDT) switch using 0.13 mu m SOI technology is presented. The switch is designed by using a series-shunt configuration with input and output matching networks. The channel length and gate bias impacts on switch performance are studied. It is found that the transistor channel length has dominant effects on both the insertion loss and isolation. The measured insertion loss of the SPDT with 0.13 mu m channel length transistor is less than 1.9 dB up to 50 GHz, while the isolation is better than 27 dB. Measured P1dB for SPDT switch is larger than 12 dBm. The active chip area of designed SPDT switch is only 0.21 x 0.19 mm(2).

引用

页码：197 / 198

页数：2

共 36 条

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