共 50 条
- [31] A timing-driven global routing algorithm considering channel density minimization for standard cell layout ISCAS 96: 1996 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - CIRCUITS AND SYSTEMS CONNECTING THE WORLD, VOL 4, 1996, : 424 - 427
- [33] A timing-driven global routing algorithm with pin assignment, block reshaping, and positioning for building block layout PROCEEDINGS OF THE ASP-DAC '98 - ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 1998 WITH EDA TECHNO FAIR '98, 1998, : 577 - 583
- [34] A timing-driven global routing algorithm with pin assignment, block reshaping, and positioning for building block layout IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 1998, E81A (12): : 2476 - 2484
- [35] Timing-driven global routing algorithm with pin assignment, block reshaping, and positioning for building block layout Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 1998, : 577 - 583
- [37] A PSO-based timing-driven Octilinear Steiner tree algorithm for VLSI routing considering bend reduction Soft Computing, 2015, 19 : 1153 - 1169
- [38] Layout-driven timing optimization by Generalized De Morgan transform ASP-DAC/VLSI DESIGN 2002: 7TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE AND 15TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS, 2002, : 647 - 654
- [39] Timing-Driven X-architecture Steiner Minimum Tree Construction Based on Social Learning Multi-Objective Particle Swarm Optimization WEB CONFERENCE 2021: COMPANION OF THE WORLD WIDE WEB CONFERENCE (WWW 2021), 2021, : 77 - 84
- [40] Post-layout timing-driven cell placement using an accurate net length model with movable Steiner points PROCEEDINGS OF THE ASP-DAC 2001: ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 2001, 2001, : 595 - 600