A Low Power, High Performance Analog Front-End Circuit for 1 V Digital Hearing Aid SoC

In this paper a low power, high performance analog front-end (AFE) circuit for digital hearing aid SoC is presented. It adopts digital-feedback-gain-control (DFGC) for accurate amplification and the multi-bit Sigma-Delta modulator technique to improve dynamic range with low power consumption. The auto gain control loop with peak-statistics-logic and DFGC can also work in variable gain control mode controlled by digital signal processor. Moreover, data weighted averaging circuit reduces nonlinearity of multi-bit Sigma-Delta technique. The analog front-end is implemented in SMIC 0.13 m 1P8M CMOS process. The measurement results show that in 1 V power supply, at 200 mV, between 100 Hz and 8 kHz, the output minimum noise floor is 120 dBm. And the maximal SNR is 88 dB, SNDR is 81 dB, total power is 180 W for a single-channel AFE, which meets the application requirement of hearing aid SoC.