A 0.5-V low power analog front-end for heart-rate detector

被引：13

作者：

Suda, Naveen ^{[1
,2
,3
]}

Nishanth, P. V. ^{[1
]}

Basak, Debajit ^{[1
,4
]}

Sharma, Durshee ^{[1
]}

Paily, Roy P. ^{[1
]}

机构：

[1] Indian Inst Technol, Dept Elect & Elect Engn, Gauhati 781039, Assam, India

[2] Tejas Networks India Pvt Ltd, Bangalore, Karnataka, India

[3] IBM India, Bangalore, Karnataka, India

[4] Indian Inst Technol Guwahati, VLSI Design Lab, Gauhati, Assam, India

来源：

ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING | 2014年 / 81卷 / 02期

关键词：

Low power; 0.5 V operation; Second order sigma delta modulator; Switched opamp; Switched capacitor filter; SIGMA-DELTA MODULATOR; SWITCHED-OPAMP; CIRCUITS; FILTER;

D O I：

10.1007/s10470-014-0402-1

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents a low power analog front-end for heart-rate detector at a supply voltage of 0.5 V in 0.18 mu m CMOS technology. A fully differential preamplifier is designed with a low power consumption of 300 nW. A 150 nW fourth order Switched-opamp switched capacitor bandpass filter is designed with passband 8-32 Hz. To digitize the analog signal, a low power second-order I I" pound ADC is designed. The dynamic range and SNR of the converter are 46 dB and 54 dB respectively and it consumes a power of 125 nW. The overall front-end system including preamplifier, SO-SC bandpass filter, I I" pound modulator and the biasing circuits are integrated and the total system consumes a power of 0.975 mu W from 0.5 V supply.

引用

页码：417 / 430

页数：14

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