Process flow development and integration of porous low k for 45 nm node

被引:0
|
作者
Naik, Mehul [1 ]
Dai, Huixiong [1 ]
Ordonio, Christopher [1 ]
Yoshida, Naomi [1 ]
Nguyen, Phong [1 ]
Fang, Hongbin [1 ]
Li, Andrew [1 ]
Yang, Hsien-Lung [1 ]
Yu, Jick [1 ]
Demos, Alex [1 ]
Okazaki, Motoya [1 ]
Thothadri, Mani [1 ]
Armacost, Michael [1 ]
Ngai, Chris [1 ]
Macwilliams, Kenneth [1 ]
机构
[1] Appl Mat Inc, Santa Clara, CA 95054 USA
来源
ADVANCED METALLIZATION CONFERENCE 2007 (AMC 2007) | 2008年 / 23卷
关键词
D O I
暂无
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
Porous low k materials are essential to meet the dielectric constant requirements for 45 and 32nm node technologies. Porous low k materials present unique integration challenges and need optimization and/or development of new processes. This paper reports on the process flow development and integration of a k similar to 2.5 PECVD porous low k. Development required in the area of resist strip, pre-metal cleans, barrier deposition, and CMP are reported. Reliability testing on k similar to 2.5 film shows equivalent results as k similar to 3.0 film.
引用
收藏
页码:371 / 377
页数:7
相关论文
共 50 条
  • [1] BEOL process integration technology for 45nm node porous low-k/copper interconnects
    Matsunaga, N
    Nakamura, N
    Higashi, K
    Yamaguchi, H
    Watanabe, T
    Akiyama, K
    Nakao, S
    Fujita, K
    Miyajima, H
    Omoto, S
    Sakata, A
    Katata, T
    Kagawa, Y
    Kawashima, H
    Enomoto, Y
    Hasegawa, T
    Shibata, H
    PROCEEDINGS OF THE IEEE 2005 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE, 2005, : 6 - 8
  • [2] 45nm node integration of low-k and ULK porous dielectrics
    van den Hoek, WGM
    SOLID STATE TECHNOLOGY, 2005, 48 (11) : 28 - +
  • [3] SOD Stack Low-k Integration for 45 nm Node and Beyond
    K. Maekawa
    H. Nagai
    M. Iwashita
    M. Muramatsu
    K. Kubota
    K. Hinata
    A.Shiota
    T. Kokubo
    M. Hattori
    K. Mishima
    H. Nagano
    M. Kodera
    K. Tokushige
    电子工业专用设备, 2005, (03) : 69 - 73
  • [4] 45nm-node BEOL integration featuring porous-ultra-low-K/Cu multilevel interconnects
    Sugiura, I
    Nakata, Y
    Misawa, N
    Otsuka, S
    Nishikawa, N
    Iba, Y
    Sugimoto, F
    Setta, Y
    Sakai, H
    Mizushima, Y
    Kotaka, Y
    Uchibori, C
    Suzuki, T
    Kitada, H
    Koura, Y
    Nakano, K
    Karasawa, T
    Ohkura, Y
    Watatani, H
    Sato, M
    Nakai, S
    Nakaishi, M
    Shimizu, N
    Fukuyama, S
    Miyajima, M
    Nakamura, T
    Yano, E
    Watanabe, K
    PROCEEDINGS OF THE IEEE 2005 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE, 2005, : 15 - 17
  • [5] Material design of porous low-k materials for 45 nm node interconnects
    Watanabe, K.
    Miyajima, H.
    Shimada, M.
    Nakamura, N.
    Shimayama, T.
    Enomoto, Y.
    Yano, H.
    Yoda, T.
    Advanced Metallization Conference 2006 (AMC 2006), 2007, : 307 - 312
  • [6] Influences of atomic hydrogen on porous low-k dielectric for 45-nm node
    Tomioka, K.
    Soda, E.
    Kobayashi, N.
    Takata, M.
    Uda, S.
    Ogushi, K.
    Yuba, Y.
    Akasaka, Y.
    THIN SOLID FILMS, 2007, 515 (12) : 5031 - 5034
  • [7] Robust 45nm porous low-k process integration with well-controlled plasma process damage and moisture uptake
    Matsunaga, Noriaki
    2006 IEEE International Conference on Integrated Circuit Design and Technology, Proceedings, 2006, : 104 - 107
  • [8] 32 nm node BEOL integration with an extreme low-k porous SiOCH dielectric k=2.3
    Hamioud, K.
    Arnal, V.
    Farcy, A.
    Jousseaume, V.
    Zenasni, A.
    Icard, B.
    Pradelles, J.
    Manakli, S.
    Brun, Ph.
    Imbert, G.
    Jayet, C.
    Assous, M.
    Maitrejean, S.
    Galpin, D.
    Monget, C.
    Guillan, J.
    Chhun, S.
    Richard, E.
    Barbier, D.
    Haond, M.
    MICROELECTRONIC ENGINEERING, 2010, 87 (03) : 316 - 320
  • [9] Integration of ALD TaN barriers in porous low-k interconnect for the 45 nm node and beyond; solution to relax electron scattering effect
    Besling, WFA
    Arnal, V
    Guillaumond, JF
    Guedj, C
    Broekaart, M
    Chapelon, LL
    Farcy, A
    Amaud, L
    Torres, J
    IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2004, TECHNICAL DIGEST, 2004, : 325 - 328
  • [10] Robust low-k diffusion barrier (k=3.5) for 45-nm node low-k (k=2.3)/Cu integration
    Yoneda, K.
    Kato, M.
    Nakao, S.
    Kondo, S.
    Matsuki, V.
    Matsushita, K.
    Ohara, N.
    Kaneko, S.
    Fukazawa, A.
    Kimura, T.
    Kamigaki, Y.
    Kobayashi, N.
    PROCEEDINGS OF THE IEEE 2006 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE, 2006, : 184 - 186