Evaluating On-Chip Interconnects for Low Operating Frequency Silicon Neuron Arrays

We present a quantitative analysis of the limits of the time-multiplexed Address Event Representation (AER) bus for on-chip connectivity of silicon neuron arrays. In particular, we evaluate its potential to support high density and low power neural arrays operating in the subthreshold regime. Our analysis shows that due to low clock frequencies when operating in the subthreshold regime, the traditional single AER bus does not scale to large neural arrays. We find that a switched mesh network improves scalability, however, a crosspoint architecture overcomes the bandwidth limitations altogether. By trading off area for improved performance, it increases the number of neurons that can be supported in a single chip neural array.