Back Gate Influence on Transistor Efficiency of SOI nMOS Ω-gate Nanowire down to 10nm Width

被引：0

作者：

Itocazu, Vitor T. ^{[1
]}

Luciano, M. Almeida ^{[1
]}

Sonnenberg, Victor ^{[1
,2
,3
]}

Agopian, Paula G. D. ^{[1
,4
]}

Barraud, Sylvain ^{[5
,6
]}

Vinet, Maud ^{[5
,6
]}

Faynot, Olivier ^{[5
,6
]}

Martino, Joao A. ^{[1
]}

机构：

[1] Univ Sao Paulo, LSI PSI USP, Sao Paulo, Brazil

[2] FATEC SP, Sao Paulo, Brazil

[3] FATEC OSASCO CEETEPS, Sao Paulo, Brazil

[4] Sao Paulo State Univ UNESP, Sao Joao Da Boa Vista, Brazil

[5] CEA, LETI, Minatec Campus, F-38054 Grenoble, France

[6] Univ Grenoble Alpes, F-38054 Grenoble, France

来源：

2017 32ND SYMPOSIUM ON MICROELECTRONICS TECHNOLOGY AND DEVICES (SBMICRO): CHIP ON THE SANDS | 2017年

基金：

巴西圣保罗研究基金会;

关键词：

SOI; Omega-Gate; Nanowire; Back gate; Transistor Efficiency;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper shows the influence of back gate bias on transistor efficiency of nMOS SOI Omega-gate nanowire, for different width and channel length. Threshold voltage and subthreshold swing present a higher variation with the back gate bias variation in wider devices. Long channel devices present better efficiency due to the better subthreshold swing, the same reason for the narrow devices have a better efficiency. Wider devices have a higher variation in efficiency when the back gate is biased. The transistor efficiency increases when the back gate is negative biased due to the better electrostatic coupling between gate and channel.

引用

页数：4

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