Latchup in Bulk FinFET Technology

被引：0

作者：

Dai, C. -T. ^{[1
,2
,3
]}

Chen, S. -H. ^{[1
]}

Linten, D. ^{[1
]}

Scholz, M. ^{[1
]}

Hellings, G. ^{[1
]}

Boschke, R. ^{[1
,2
]}

Karp, J. ^{[4
]}

Hart, M. ^{[4
]}

Groeseneken, G. ^{[1
,2
]}

Ker, M. -D. ^{[3
]}

Mocuta, A. ^{[1
]}

Horiguchi, N. ^{[1
]}

机构：

[1] IMEC, Kapeldreef 75, B-3001 Leuven, Belgium

[2] Katholieke Univ Leuven, Elect Engn Dept, B-3001 Leuven, Belgium

[3] Natl Chiao Tung Univ, Inst Elect, Hsinchu 30010, Taiwan

[4] Xilinx Inc, 2100 Log Dr, San Jose, CA 95124 USA

来源：

2017 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS) | 2017年

关键词：

Latchup; bulk FinFET; silicon control rectifier (SCR);

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Latchup (LU) had been considered to be less important in advanced CMOS technologies. However, I/O interface and analog applications can still operate at high voltage (e.g., 1.8V or 3.3V) in sub-20nm bulk FinFET technologies. LU threats are never eliminated and the sensitivity towards LU is increased in bulk FinFET technology.

引用

页数：3

共 50 条

[41] Designing with FinFET Technology
Marshall, Andrew
2014 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC), 2014, : 30 - 31
[42] Stringer Gate FinFET on Bulk Substrate
Han, Jin-Woo
Wong, Hiu Yung
Moon, Dong-Il
Braga, Nelson
Meyyappan, M.
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2016, 63 (09) : 3432 - 3438
[43] SOI FinFET versus Bulk FinFET for 10nm and below
Hook, Terence B.
Allibert, F.
Balakrishnan, K.
Doris, Bruce
Guo, Dechao
Mavilla, Narasimha
Nowak, E.
Tsutsui, G.
Southwick, R.
Strane, J.
Sun, Xin
2014 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2014,
[44] Review of FINFET technology
Jurczak, M.
Collaert, N.
Veloso, A.
Hoffmann, T.
Biesemans, S.
2009 IEEE INTERNATIONAL SOI CONFERENCE, 2009, : 3 - 6
[45] Soft Error Rate Predictions for Terrestrial Neutrons at the 3-nm Bulk FinFET Technology
Xiong, Yoni
Chiang, Yueh
Pieper, Nicholas J.
Ball, Dennis R.
Bhuva, Bharat L.
2023 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM, IRPS, 2023,
[46] Towards Optimal ESD Diodes in Next Generation Bulk FinFET and GAA NW Technology Nodes
Chen, S. -H.
Hellings, G.
Linten, D.
Chiarella, T.
Mertens, H.
Boschke, R.
Mitard, J.
Kubicek, S.
Ritzenthaler, R.
Bury, E.
Wang, N.
Groeseneken, G.
Mocuta, A.
Horiguchi, N.
2017 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2017,
[47] Impact of Through Silicon Via Induced Mechanical Stress on Fully Depleted Bulk FinFET Technology
Guo, W.
Van der Plas, G.
Ivankovic, A.
Cherman, V.
Eneman, G.
De Wachter, B.
Togo, M.
Redolfi, A.
Kubicek, S.
Civale, Y.
Chiarella, T.
Vandevelde, B.
Croes, K.
De Wolf, I.
Debusschere, I.
Mercha, A.
Thean, A.
Beyer, G.
Swinnen, B.
Beyne, E.
2012 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2012,
[48] Deep N-well Induced Latch-up Challenges in Bulk FinFET Technology
Huang, Chien-Yao
Su, Yu-Ti
Chang, Tzu-Heng
Hsu, Chia-Wei
Lee, Jam-Wem
Chen, Kuo-Ji
Song, Ming-Hsiang
2017 39TH ELECTRICAL OVERSTRESS/ELECTROSTATIC DISCHARGE SYMPOSIUM (EOS/ESD), 2017,
[49] Evaluation of Threshold Frequencies for Logic Single-Event Upsets at Bulk FinFET Technology Nodes
Xiong, Yoni
Pieper, Nicholas J.
Kronenberg, Jenna B.
Chiang, Yueh
Fung, Rita
Wen, Shi-Jie
Bhuva, Bharat L.
IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2024, 71 (08) : 1675 - 1681
[50] IMPROVEMENT OF LATCHUP HARDNESS BY GEOMETRY AND TECHNOLOGY TUNING
MAZURE, C
RECZEK, W
TAKACS, D
WINNERL, J
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1988, 35 (10) : 1609 - 1615

← 1 2 3 4 5 →