Latchup in Bulk FinFET Technology

被引：0

作者：

Dai, C. -T. ^{[1
,2
,3
]}

Chen, S. -H. ^{[1
]}

Linten, D. ^{[1
]}

Scholz, M. ^{[1
]}

Hellings, G. ^{[1
]}

Boschke, R. ^{[1
,2
]}

Karp, J. ^{[4
]}

Hart, M. ^{[4
]}

Groeseneken, G. ^{[1
,2
]}

Ker, M. -D. ^{[3
]}

Mocuta, A. ^{[1
]}

Horiguchi, N. ^{[1
]}

机构：

[1] IMEC, Kapeldreef 75, B-3001 Leuven, Belgium

[2] Katholieke Univ Leuven, Elect Engn Dept, B-3001 Leuven, Belgium

[3] Natl Chiao Tung Univ, Inst Elect, Hsinchu 30010, Taiwan

[4] Xilinx Inc, 2100 Log Dr, San Jose, CA 95124 USA

来源：

2017 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS) | 2017年

关键词：

Latchup; bulk FinFET; silicon control rectifier (SCR);

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Latchup (LU) had been considered to be less important in advanced CMOS technologies. However, I/O interface and analog applications can still operate at high voltage (e.g., 1.8V or 3.3V) in sub-20nm bulk FinFET technologies. LU threats are never eliminated and the sensitivity towards LU is increased in bulk FinFET technology.

引用

页数：3

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