Efficient partitioning method for distributed logic simulation of VLSI circuits

被引：2

作者：

Guettaf, A ^{[1
]}

Bazargan-Sabet, P ^{[1
]}

机构：

[1] Univ Paris 06, Lab ASIM, LIP6, CAO,VLSI, F-75252 Paris 05, France

来源：

31ST ANNUAL SIMULATION SYMPOSIUM, PROCEEDINGS | 1998年

关键词：

D O I：

10.1109/SIMSYM.1998.668488

中图分类号：

TP39 [计算机的应用];

学科分类号：

081203 ; 0835 ;

摘要：

Distributed simulation is expected to provide a significant speed up to simulation run time. Partitioning and load balancing are very influencing factors for speed up. This paper presents an efficient partitioning method for distributed VLSI circuits simulation. The main features of this method are the use of a logic replication algorithm: a realistic cost function based on precalculated activity of the circuit using a probabilistic algorithm, and a the balance between execution cost and communication cost. A distributed simulator based on a conservative synchronization method has been used to evaluate the performance of the partitioning.

引用

页码：196 / 201

页数：6

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