共 50 条
- [41] Non-scan design for testable data paths using thru operation PROCEEDINGS OF THE ASP-DAC '97 - ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 1997, 1996, : 313 - 318
- [42] A SoC test strategy based on a non-scan DFT method PROCEEDINGS OF THE 11TH ASIAN TEST SYMPOSIUM (ATS 02), 2002, : 305 - 310
- [43] TESTABILITY-BASED PARTIAL SCAN ANALYSIS JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 1995, 7 (1-2): : 61 - 70
- [44] LFSR Based Secured Scan design Testability Techniques 7TH INTERNATIONAL CONFERENCE ON ADVANCES IN COMPUTING & COMMUNICATIONS (ICACC-2017), 2017, 115 : 174 - 181
- [45] ANALYSIS OF SYNCHRONOUS GENERATOR SEQUENTIAL SHORT CIRCUITS PROCEEDINGS OF THE INSTITUTION OF ELECTRICAL ENGINEERS-LONDON, 1977, 124 (06): : 549 - 553
- [46] Design for Delay Fault Testability of Dual Circuits Using Master and Slave Scan Paths IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2009, E92D (03): : 433 - 442
- [47] A partial scan design approach based on register-transfer level testability analysis IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 1996, E79D (10): : 1436 - 1442
- [48] Incremental Testability Analysis for Partial Scan Selection and Design Transformations Journal of Electronic Testing, 1999, 14 : 103 - 113
- [49] Partial scan design approach based on register-transfer level testability analysis IEICE Trans Inf Syst, 10 (1436-1442):
- [50] Incremental testability analysis for partial scan selection and design transformations JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 1999, 14 (1-2): : 103 - 113