共 50 条
- [34] Survivable synchronous sequential circuits design BEC 2002: PROCEEDINGS OF THE 8TH BIENNIAL BALTIC ELECTRONIC CONFERENCE, 2002, : 133 - 136
- [35] DESIGN FOR TESTABILITY USING INCOMPLETE SCAN PATH AND TESTABILITY ANALYSIS SIEMENS FORSCHUNGS-UND ENTWICKLUNGSBERICHTE-SIEMENS RESEARCH AND DEVELOPMENT REPORTS, 1984, 13 (02): : 56 - 61
- [38] Design-for-Test Methodology for Non-Scan At-Speed Testing 2011 DESIGN, AUTOMATION & TEST IN EUROPE (DATE), 2011, : 191 - 196
- [39] On the (non-)resetability of synchronous sequential circuits 14TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 1996, : 240 - 245