共 50 条
- [21] Peak power minimization through datapath scheduling ISVLSI 2003: IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI, PROCEEDINGS: NEW TRENDS AND TECHNOLOGIES FOR VLSI SYSTEMS DESIGN, 2003, : 121 - 126
- [22] Power Scheduling for MSE Minimization with Peak and Average Power Constraints 2014 48TH ANNUAL CONFERENCE ON INFORMATION SCIENCES AND SYSTEMS (CISS), 2014,
- [24] Circuit-based preprocessing of ILP and its applications in leakage minimization and power estimation IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN: VLSI IN COMPUTERS & PROCESSORS, PROCEEDINGS, 2004, : 387 - 392
- [26] Low-power high-level synthesis using latches PROCEEDINGS OF THE ASP-DAC 2001: ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 2001, 2001, : 462 - 465
- [27] Quantitative Performance and Power Analysis of LTE using High Level Synthesis PROCEEDINGS OF 2015 IEEE 11TH INTERNATIONAL CONFERENCE ON ASIC (ASICON), 2015,
- [28] Power-conscious high level synthesis using loop folding DESIGN AUTOMATION CONFERENCE - PROCEEDINGS 1997, 1997, : 441 - 445
- [29] A SAT BASED SCHEDULING TECHNIQUE FOR PEAK POWER MINIMIZATION 3RD INTERNATIONAL CONFERENCE ON RECENT TRENDS IN COMPUTING 2015 (ICRTC-2015), 2015, 57 : 929 - 935
- [30] On Minimization of Peak Power for Scan Circuit during Test ETS 2009: EUROPEAN TEST SYMPOSIUM, PROCEEDINGS, 2009, : 25 - +