Accurate TSV Number Minimization in High-Level Synthesis

被引：0

作者：

Lee, Chih-Hung ^{[1
]}

Huang, Shih-Hsu ^{[1
]}

Cheng, Chun-Hua ^{[1
]}

机构：

[1] Chung Yuan Christian Univ, Dept Elect Engn, Chungli 320, Taiwan

来源：

JOURNAL OF INFORMATION SCIENCE AND ENGINEERING | 2011年 / 27卷 / 05期

关键词：

electronic design automation; high-level synthesis; three dimensional integration circuits; layer assignment; through silicon via; BINDING;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

Recent progress in process technology makes it possible to vertically stack multiple integrated chips. In three dimensional integration circuits (3D ICs), through silicon vias (TSVs) are used to communicate signals between layers. However, TSVs act as obstacles during placement and routing and have a negative impact on chip yield. Therefore, TSV number minimization is an important topic in 3D IC design. However, previous high-level synthesis approach only tries to maximize the number of same-layer operation-level data-transfers. In fact, a TSV should correspond to a cross-layer resource-level data-transfer. Therefore, in this paper, we propose an integer linear programming (ILP) approach to perform TSV number minimization by minimizing the number of cross-layer resource-level data-transfers. Experimental results consistently show that our approach is more effective than the previous approach in TSV number minimization.

引用

页码：1527 / 1543

页数：17

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