Modeling simultaneous switching noise-induced jitter for system-on-chip phase-locked loops

Phase-Locked Loops (PLLs) are versatile modules for synchronization and applications such as high-speed serial interfaces in System-on-Chips (SoCs). Their precisions are critical to proper functioning of the SoCs. Intermodule interference such as simultaneous switching noise (SSN) is time-varying, where the stationary assumption in conventional jitter analysis does not apply. We propose a methodology to compute PLL jitter by investigating the harmonic relations between the PLL system with SSN. This provides statistical analysis over many VCO design parameters, SoC modules and noise barrier configurations. Its accuracy and efficiency are compared against circuit simulations.