Power consumption reduction using dynamic control of micro processor performance

被引:0
|
作者
Rios-Arambula, D [1 ]
Buhrig, A [1 ]
Renaudin, M [1 ]
机构
[1] TIMA Lab, F-38031 Grenoble, France
来源
INTEGRATED CIRCUIT AND SYSTEM DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION | 2005年 / 3728卷
关键词
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
An alternative way to reduce power consumption using dynamic voltage scaling is presented. The originality of this approach is the modeling and simulation of a system where each application indicates its performance needs (in MIPS) to the operating system, which in turn is able to know the global speed requirements of the system to meet all real time application deadlines. To achieve this level of control, a co-processor is described, that receives a set point command from the OS, and manages a DC/DC converter implemented as a charge pump, in order to have the system speed fitting this set point. This architecture is especially suited for asynchronous processors but can be adapted for synchronous ones as well.
引用
收藏
页码:10 / 18
页数:9
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