Analytical model for the propagation delay of through silicon vias

被引：22
|
作者：
Khalil, DiaaEldin [1 ]
Ismail, Yehea [1 ]
Khellah, Muhammad [2 ]
Karnik, Tanay [2 ]
De, Vivek [2 ]
机构：
[1] Northwestern Univ, EECS Dept, Evanston, IL 60208 USA
[2] Intel Corp, Circuits Res Lab, Santa Clara, CA USA
来源：
ISQED 2008: PROCEEDINGS OF THE NINTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN | 2008年
关键词：
D O I：
10.1109/ISQED.2008.128
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper explores the modeling of the propagation delay of through silicon Was (TSVs) in 3D integrated circuits. The electrical characteristics and models of the TSVs are very crucial in enabling the analysis and CAD in 3D integrated circuits. In this paper, an analytical model for the propagation delay of the TSV as a function of its physical dimensions is proposed The presented analytical model is in great agreement with simulations using electromagnetic field solver and lossy transmission line circuit model. Compared to earlier interconnect models, the presented analytical model provides higher accuracy and fidelity in addition to its simplicity. Hence, the presented analytical model is very useful in the analysis of 3D integrated circuits.
引用
收藏
页码：553 / +
页数：2
相关论文
共 50 条
  • [21] An analytical propagation delay model with power supply noise effects
    Pude, Mork
    Washburn, Clyde
    Mukund, P. R.
    Abe, Kouichi
    Nishi, Yoshinori
    2006 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, PROCEEDINGS, 2006, : 629 - 632
  • [22] Tutorial on forming through-silicon vias
    Burkett, Susan L.
    Jordan, Matthew B.
    Schmitt, Rebecca P.
    Menk, Lyle A.
    Hollowell, Andrew E.
    JOURNAL OF VACUUM SCIENCE & TECHNOLOGY A, 2020, 38 (03):
  • [23] An Anisotropic Equivalent Thermal Model for Shield Differential Through-Silicon Vias
    Shan, Guangbao
    Li, Guoliang
    Chen, Dongdong
    Yang, Zifeng
    Li, Di
    Yang, Yintang
    MICROMACHINES, 2021, 12 (10)
  • [24] Process integration for through-silicon vias
    Spiesshoefer, S
    Rahman, Z
    Vangara, G
    Polamreddy, S
    Burkett, S
    Schaper, L
    JOURNAL OF VACUUM SCIENCE & TECHNOLOGY A, 2005, 23 (04): : 824 - 829
  • [25] Applying a Physics-Based Via Model for the Simulation of Through Silicon Vias
    Dahl, David
    Duan, Xiaomin
    Beyreuther, Anne
    Ndip, Ivan
    Lang, Klaus-Dieter
    Schuster, Christian
    2013 IEEE 22ND CONFERENCE ON ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING AND SYSTEMS (EPEPS), 2013, : 65 - 68
  • [26] HIGH FREQUENCY CHARACTERIZATION OF SILICON SUBSTRATE AND THROUGH SILICON VIAS
    Duan, Xiaomin
    Boettcher, Mathias
    Dahl, David
    Schuster, Christian
    Tschoban, Christian
    Ndip, Ivan
    Lang, Klaus-Dieter
    2016 IEEE 66TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2016, : 1544 - 1550
  • [27] On the Futility of Thermal Through-Silicon-Vias
    Chou, Chung-Han
    Tsai, Nien-Yu
    Yu, Hao
    Shi, Yiyu
    Chien, Jui-Hung
    Chang, Shih-Chieh
    2013 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION, AND TEST (VLSI-DAT), 2013,
  • [28] MULTISCALE MODELS FOR ELECTROPLATING OF THROUGH SILICON VIAS
    Khoo, K. H.
    Lai MingRui
    Ramanarayan, H.
    Hongmei, J.
    Wu, S.
    Joshi, C. A.
    Mangipudi, K. R.
    Cheng, J. J.
    Quek, S. S.
    Wu, D. T.
    Sridhar, N.
    Bharathi, M. S.
    2018 INTERNATIONAL WAFER LEVEL PACKAGING CONFERENCE (IWLPC), 2018,
  • [29] Test Structures for Characterization of Through Silicon Vias
    Stucchi, M.
    Perry, D.
    Katti, G.
    Dehaene, W.
    2010 INTERNATIONAL CONFERENCE ON MICROELECTRONIC TEST STRUCTURES, 23RD IEEE ICMTS CONFERENCE PROCEEDINGS, 2010, : 130 - 134
  • [30] On the Futility of Thermal Through-Silicon-Vias
    Chou, Chung-Han
    Tsai, Nien-Yu
    Yu, Hao
    Shi, Yiyu
    Chien, Jui-Hung
    Chang, Shih-Chieh
    2013 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION, AND TEST (VLSI-DAT), 2013,
12345