An analytical propagation delay model with power supply noise effects

被引：0
|
作者：
Pude, Mork [1 ]
Washburn, Clyde
Mukund, P. R.
Abe, Kouichi
Nishi, Yoshinori
机构：
[1] Rochester Inst Technol, Dept Elect Engn, Rochester, NY 14623 USA
[2] Kawasaki Microelect America Inc, Mixed Signal IP Dev, San Jose, CA USA
来源：
2006 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, PROCEEDINGS | 2006年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper presents an analytical model for CMOS logic propagation delay which includes the effect of power supply noise. Using the nth power law model of MOSFETs, two scenarios are addressed: self-induced power supply noise and globally-induced power supply noise. The analytical model is verified in simulation for both cases. The self-induced noise model matches simulation to within 0.36%. The globally-induced noise model matches simulation to within 5% for typical input rise time values and never more than 15% under extreme conditions.
引用
收藏
页码：629 / 632
页数：4
相关论文
共 50 条
  • [1] Power supply noise in delay testing
    Wang, Jing
    Walker, D. M. H.
    Majhi, Ananta
    Kruseman, Bram
    Gronthoud, Guido
    Villagra, Luis Elvira
    van de Wiel, Paul
    Eichenberger, Stefan
    2006 IEEE INTERNATIONAL TEST CONFERENCE, VOLS 1 AND 2, 2006, : 510 - +
  • [2] Modeling power supply noise in delay testing
    Wang, Jing
    Walker, Duncan M.
    Lu, Xiang
    Majhi, Ananta
    Kruseman, Bram
    Gronthoud, Guido
    Villagra, Luis Elvira
    van de Wiel, Paul J. A. M.
    Eichenberger, Stefan
    IEEE DESIGN & TEST OF COMPUTERS, 2007, 24 (03): : 226 - 234
  • [3] Static timing analysis including power supply noise effect on propagation delay in VLSI circuits
    Bai, G
    Bobba, S
    Hajj, IN
    38TH DESIGN AUTOMATION CONFERENCE PROCEEDINGS 2001, 2001, : 295 - 300
  • [4] Power supply noise in accurate delay model for the sub-threshold domain
    Corsonello, Pasquale
    Frustaci, Fabio
    Perri, Stefania
    INTEGRATION-THE VLSI JOURNAL, 2015, 50 : 127 - 136
  • [5] Analytical model for the propagation delay of through silicon vias
    Khalil, DiaaEldin
    Ismail, Yehea
    Khellah, Muhammad
    Karnik, Tanay
    De, Vivek
    ISQED 2008: PROCEEDINGS OF THE NINTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, 2008, : 553 - +
  • [6] Power supply effects on noise performance
    Gray, N
    ELECTRONIC DESIGN, 2001, 49 (09) : U3 - U4
  • [7] Estimating Power Supply Noise and Its Impact on Path Delay
    Rao, Sushmita Kadiyala
    Sathyanarayana, Chaitra
    Kallianpur, Ajay
    Robucci, Ryan
    Patel, Chintan
    2012 IEEE 30TH VLSI TEST SYMPOSIUM (VTS), 2012, : 276 - 281
  • [8] Static compaction of delay tests considering power supply noise
    Wang, J
    Lu, X
    Qiu, WQ
    Yue, ZD
    Fancler, S
    Shi, WP
    Walker, DMH
    23RD IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 2005, : 235 - 240
  • [9] Pseudo-Functional Testing for Small Delay Defects Considering Power Supply Noise Effects
    Yuan, Feng
    Liu, Xiao
    Xu, Qiang
    2011 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD), 2011, : 34 - 39
  • [10] Noise propagation effects in power supply distribution systems for high-energy physics experiments
    Arteche, F.
    Rivetta, C.
    Iglesias, M.
    Echeverria, I.
    Pradas, A.
    Arcega, F. J.
    JOURNAL OF INSTRUMENTATION, 2017, 12
12345