High Frame Rate VGA CMOS Image Sensor using Two Step Single Slope ADCs

被引：0

作者：

Park, Himchan ^{[1
]}

Lee, Junan ^{[1
]}

Kim, Jinwoo ^{[1
]}

Shin, Yongsik ^{[1
]}

Burm, Jinwook ^{[1
]}

机构：

[1] Sogang Univ, Dept Elect Engn, Seoul, South Korea

来源：

2016 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS) | 2016年

基金：

新加坡国家研究基金会;

关键词：

CnIumn-parallel ADC; single-slope(SS) ADC; Two-step ADC; Non memory capacitor;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A column-parallel two step Single Slope Analog-to-Digital Converter (SS ADC) for high frame rate VGA CMOS Image Sensor. The proposed circuit improves the sampling rate while maintaining the architecture of the conventional SS ADC for high frame rate CIS. The proposed structure does not have analog memory capacitor for storing the value of the first ramp step. The proposed two-step SS ADC has a 12 hit resolution and conversion time of 6.3 mu s at 62.5MHz clock frequency. The VGA CIS using two step SS ADC has the maximum frame rate of upto 320 frames/s.

引用

页码：571 / 572

页数：2

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