Reduction of I/O Power Using Energy Efficient HSTL I/O Standard in Vedic Multiplier on FPGA

This design is implemented on 90nm Virtex (4xc4vfx12), 65nm Virtex 5(xc5vlx20t2ff323), and 40nm Virtex 6(xc6vcx75t). I/O power is the major contributor in dynamic power dissipation in VLSI design. In this work, different I/O standard of HSTL (High Speed Transceiver Logic) is taken under consideration in order to find the most energy efficient I/O standard from I/O power perspective. I/O power is the sum total of power dissipation by both input and output port in any VLSI circuit design. Selection of I/O standard plays an important role in energy efficient design. I/O power was greater than leakage power when technology was not less than 90nm. But, from 65nm technology onward, leakage power dissipation starts dominating I/O power dissipation. There is 72-29 % and 65-28% decrease in I/O power dissipation on 90nm and 40nm respectively, when we are using HSTL_II, HSTL_II_ 18 and HSTL_II_DCI IO standard in place of HSTL_II_DCI_18.