Automated synthesis of large phase shifters for built-in self-test

被引:48
|
作者
Rajski, J [1 ]
Tamarapalli, N [1 ]
Tyszer, J [1 ]
机构
[1] Mentor Graph Corp, Wilsonville, OR 97070 USA
关键词
D O I
10.1109/TEST.1998.743303
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
The paper introduces a new algorithm for the automated synthesis of phase shifters - circuits used to remove effects of structural dependencies featured by two-dimensional test generators. The algorithms presented in the paper synthesize in a time-efficient manner very large and fast phase shifters for built-in self-test environment, with guaranteed minimal phaseshifts between scan chains, and very low delay and area of virtually one 2-way XOR gate per channel.
引用
收藏
页码:1047 / 1056
页数:10
相关论文
共 50 条
  • [41] CELLULAR AUTOMATA CIRCUITS FOR BUILT-IN SELF-TEST
    HORTENSIUS, PD
    MCLEOD, RD
    PODAIMA, BW
    IBM JOURNAL OF RESEARCH AND DEVELOPMENT, 1990, 34 (2-3) : 389 - 405
  • [42] BUILT-IN CHECKING OF THE CORRECT SELF-TEST SIGNATURE
    MCANNEY, WH
    SAVIR, J
    IEEE TRANSACTIONS ON COMPUTERS, 1988, 37 (09) : 1142 - 1145
  • [43] BUILT-IN SYNTHESIZED SWEEPER SELF-TEST AND ADJUSTMENTS
    SEIBEL, MJ
    HEWLETT-PACKARD JOURNAL, 1991, 42 (02): : 17 - 23
  • [44] BUILT-IN SELF-TEST - PASS OR FAIL - INTRODUCTION
    SEDMAK, RM
    IEEE DESIGN & TEST OF COMPUTERS, 1985, 2 (02): : 17 - 19
  • [45] Online Built-In Self-Test Architecture for Automated Testing of a Solar Tracking Equipment
    Jurj, Sorin Liviu
    Rotar, Raul
    Opritoiu, Flavius
    Vladutiu, Mircea
    2020 20TH IEEE INTERNATIONAL CONFERENCE ON ENVIRONMENT AND ELECTRICAL ENGINEERING AND 2020 4TH IEEE INDUSTRIAL AND COMMERCIAL POWER SYSTEMS EUROPE (EEEIC/I&CPS EUROPE), 2020,
  • [46] A Hybrid Built-In Self-Test Scheme for DRAMs
    Yang, Chi-Chun
    Li, Jin-Fu
    Yu, Yun-Chao
    Wu, Kuan-Te
    Lo, Chih-Yen
    Chen, Chao-Hsun
    Lai, Jenn-Shiang
    Kwai, Ding-Ming
    Chou, Yung-Fa
    2015 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT), 2015,
  • [47] BUILT-IN SELF-TEST DESIGN OF SEMICONDUCTOR MEMORY
    RAJASHEKHARA, TN
    INTERNATIONAL JOURNAL OF ELECTRONICS, 1991, 70 (03) : 645 - 649
  • [48] THE REAL-ESTATE FOR BUILT-IN SELF-TEST
    OHR, S
    COMPUTER DESIGN, 1994, 33 (11): : 142 - &
  • [49] Arithmetic pattern generators for built-in self-test
    Stroele, AP
    INTERNATIONAL CONFERENCE ON COMPUTER DESIGN - VLSI IN COMPUTERS AND PROCESSORS, PROCEEDINGS, 1996, : 131 - 134
  • [50] A programmable built-in self-test for embedded DRAMs
    Banerjee, S
    Chowdhury, DR
    Bhattacharya, BB
    2005 IEEE INTERNATIONAL WORKSHOP ON MEMORY TECHNOLOGY, DESIGN, AND TESTING - PROCEEDINGS, 2005, : 58 - 63