Low noise preamplifier design for nerve cuff electrode recording systems

This paper discusses certain crucial issues involved in the design of a preamplifier for an implantable neuralprosthesis. The preamplifier has a nominal gain of 100, a bandwidth of 15KHz and is required to combine very low noise with low power consumption. In particular, due to the low frequencies involved, 1/f noise assumes great significance. We consider three possible architectures for the input stage of the preamplifier: (a) BICMOS and CMOS in (b) weak and (c) strong inversion. We demonstrate that although the CMOS amplifiers can approach the performance of the BICMOS circuit, this is only possible at the cost of greater power consumption and enormously increased circuit area. Against these arguments must be set the greater cost of a BICMOS process.