Validating the Performance of a 32nm CMOS High Speed Serial Link Receiver with Adaptive Equalization and Baud-Rate Clock Data Recovery

On-Die features available for validation and test on an integrated circuit play a major role in evaluating the performance of the functionality being realized by the circuit in a post-silicon environment and can considerably reduce time to market of the end-product. In the case of high-speed 10, it is also important to note that the type of on-die hooks required to debug and validate the performance and robustness of the design depend on several factors, of which the type of I/O architecture chosen plays a key role. In order to support high data rates, the serial I/O design in this paper implements a receiver with adaptive equalization engine for the compensation of inter-symbol interference (lSI) and real-time environmental changes (temperature and voltage). This paper describes the debug hooks and their usage models in such a high-speed I/O designed using a 32nm CMOS process. These hooks have been tested in the lab and proven to be very useful. While the main focus of the paper is to describe the hooks, how they are used in the lab for observing the robustness in the dynamic behavior of the adaptive loops and the measurement results; the reader is also provided with a brief insight into the equations describing the loops behavior together with a description of the loops implementation details.