A Low Noise Fault Tolerant Radiation Hardened 2.56 Gbps Clock-Data Recovery Circuit with High Speed Feed Forward Correction in 65 nm CMOS

被引：5

作者：

Prinzie, Jeffrey ^{[1
,2
]}

Kulis, Szymon ^{[2
]}

Leitao, Pedro ^{[2
]}

Francisco, Rui ^{[2
]}

De Smedt, Valentijn ^{[1
]}

Moreira, Paulo ^{[2
]}

Leroux, Paul ^{[1
,2
]}

机构：

[1] KU Leuven Univ, ESAT ADVISE Res Lab, Leuven, Belgium

[2] CERN, European Ctr Nucl Res, Geneva, Switzerland

来源：

2019 IEEE 10TH LATIN AMERICAN SYMPOSIUM ON CIRCUITS & SYSTEMS (LASCAS) | 2019年

关键词：

CDR; Single-Event Upsets; Radiation hardening; jitter; phase noise; clock recovery; PHASE;

D O I：

10.1109/lascas.2019.8667542

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A fault tolerant, radiation hardened Clock and Data Recovery (CDR) architecture is presented for high-energy physics and space applications. The CDR employs a novel soft-error tolerant Voltage Controlled Oscillator (VCO) and includes a high-speed feed-forward path to stabilize the CDR to compensate for an additional pole in the VCO to harden it against ionizing particles. The CDR has a data rate of 2.56 Gbps and uses In-Phase/Quadrature (IQ) clocks in combination with a frequency detector (FD) to increase the pull-in range. The circuit was designed in a 65 nm CMOS technology and has a core power consumption of only 34 mW.

引用

页码：65 / 68

页数：4

共 7 条

[1] A Low Noise Fault Tolerant Radiation Hardened 2.56 Gbps Clock-Data Recovery Circuit With High Speed Feed Forward Correction in 65 nm CMOS
Biereigel, Stefan
Kulis, Szymon
Leitao, Pedro
Francisco, Rui
Moreira, Paulo
Leroux, Paul
Prinzie, Jeffrey
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2020, 67 (05) : 1438 - 1446
[2] A 6-Gbps dual-mode digital clock and data recovery circuit in a 65-nm CMOS technology
Jeon, Min-Ki
Yoo, Changsik
ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2015, 85 (01) : 209 - 215
[3] A 6-Gbps dual-mode digital clock and data recovery circuit in a 65-nm CMOS technology
Min-Ki Jeon
Changsik Yoo
Analog Integrated Circuits and Signal Processing, 2015, 85 : 209 - 215
[4] A Robust High Speed Serial PHY Architecture With Feed-Forward Correction Clock and Data Recovery
Redman-White, William
Bugbee, Martin
Dobbs, Steve
Wu, Xinyan
Balmford, Richard
Nuttgens, Jonah
Kiani, Umer Salim
Clegg, Richard
den Besten, Gerrit W.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2009, 44 (07) : 1914 - 1926
[5] High-speed Clock and Data Recovery System with Segmented Slew-rate Control Circuit for High-linearity in 65 nm CMOS Process
Min, Kyunghwan
Lee, Sanggeun
Oh, Taehyoun
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2021, 21 (03) : 199 - 205
[6] A 10Gbps Half-Rate Digital Clock and Data Recovery Circuit for 60GHz Receiver in 65nm CMOS
Liu, Zhi-Ran
Zheng-Song
Wu, Ying-Hang
Li, Yu-Tian
Chi, Bao-Yong
2016 13TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT), 2016, : 554 - 556
[7] An Ultra-Low Voltage, Low-Noise, High Linearity 900-MHz Receiver With Digitally Calibrated In-Band Feed-Forward Interferer Cancellation in 65-nm CMOS
Balankutty, Ajay
Kinget, Peter R.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2011, 46 (10) : 2268 - 2283

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