Design of a Radiation Hardened Latch for Low-power Circuits

被引：30

作者：

Liang, Huaguo ^{[1
]}

Wang, Zhi ^{[1
]}

Huang, Zhengfeng ^{[1
]}

Yan, Aibin ^{[2
]}

机构：

[1] Hefei Univ Technol, Sch Elect Sci & Appl Phys, Hefei 230009, Peoples R China

[2] Hefei Univ Technol, Sch Comp & Informat, Hefei 230009, Peoples R China

来源：

2014 IEEE 23RD ASIAN TEST SYMPOSIUM (ATS) | 2014年

关键词：

Single event upset (SEU); Soft errors; C-element; Transient fault; Hardened latch; TOLERANT LATCH; LOW-COST; SOFT ERRORS; HIGH-PERFORMANCE;

D O I：

10.1109/ATS.2014.16

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

As technology node entered the era of nanotechnology, a latch is much more susceptible to soft errors caused by energetic particles in space radiation environment. In order to enhance the Single Event Upset (SEU)-tolerance capability of a latch, this paper presents an interlocking soft error hardened latch (ISEHL) which is suitable for low-power circuits. The proposed latch is based on three C-elements which are errors tolerable, and the logic state of each C-element is determined by the output state of two other C-elements, which constitute an interlocking soft error hardened latch. The simulation results show that the proposed ISEHL latch can not only be applied to clock-gating circuits but also perform with 41% power as well as 95% Power Delay Product (PDP) saving as comparing with the FERST latch which performs an equivalent superior SEU-tolerance ability.

引用

页码：19 / 24

页数：6

共 50 条

[31] Low-power and low-voltage D-latch
Nanyang Technological Univ, Singapore, Singapore
Electron Lett, 7 (641-642):
[32] Nonvolatile Radiation Hardened DICE Latch
Pang, Tingting
Kang, Wang
Ran, Yi
Zhang, Youguang
Lv, Weifeng
Zhao, Weisheng
2015 15TH NON-VOLATILE MEMORY TECHNOLOGY SYMPOSIUM (NVMTS), 2015,
[33] Asynchronous design for high-speed and low-power circuits
Beerel, Peter A.
INTEGRATED CIRCUIT AND SYSTEM DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION, 2006, 4148 : 669 - 669
[34] Glitch-conscious low-power design of arithmetic circuits
Eriksson, H
Larsson-Edefors, P
2004 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 2, PROCEEDINGS, 2004, : 281 - 284
[35] Low-Power Radiation Hardened 12T Memory Cell Design in 65 nm CMOS Process
Huang Z.
Li X.
Lu Y.
Ouyang Y.
Fang X.
Yi M.
Liang H.
Ni T.
Jisuanji Fuzhu Sheji Yu Tuxingxue Xuebao/Journal of Computer-Aided Design and Computer Graphics, 2019, 31 (03): : 504 - 512
[36] Design and Analysis of Low-Power Protection Circuits for LDO Regulators
Deb, Arnab
Selvakumar, David
Mervin, J.
Ghosh, Anurupa
EMERGING VLSI DEVICES, CIRCUITS AND ARCHITECTURES, VDAT 2023, 2025, 1234 : 197 - 213
[37] CNTFET based radiation hardened latch
Shakeel S.
Alam N.
Alam, Naushad (itsnaushad@rediffmail.com), 1600, Taylor and Francis Ltd. (18): : 199 - 208
[38] Reconfigurable latch controllers for low power asynchronous circuits
Lewis, M
Garside, J
Brackenbury, L
FIFTH INTERNATIONAL SYMPOSIUM ON ADVANCED RESEARCH IN ASYNCHRONOUS CIRCUITS AND SYSTEMS - PROCEEDINGS, 1999, : 27 - 35
[39] RADIATION EFFECTS ON LOW-POWER SCHOTTKY DIGITAL INTEGRATED-CIRCUITS
COOPER, MS
IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 1976, 23 (01) : 853 - 859
[40] Low-power latch comparator with accurate hysteresis control
Khanfir, Leila
Mouine, Jaouhar
JOURNAL OF ELECTRICAL ENGINEERING-ELEKTROTECHNICKY CASOPIS, 2020, 71 (06): : 379 - 387

← 1 2 3 4 5 →