Hardware Implementation of Single Iterated Multiplicative Inverse Square Root

被引:1
|
作者
Luo, Jun [1 ,2 ]
Huang, Qijun [2 ]
Luo, Hongwei [1 ]
Zhi, Yue [1 ]
Wang, Xiaoqiang [1 ]
机构
[1] China Elect Prod Reliabil & Environm Testing Res, 110 Dongguanzhuang Rd, Guangzhou, Guangdong, Peoples R China
[2] Wuhan Univ, Dept Phys & Technol, 16 Luojia Shan, Wuhan, Hubei, Peoples R China
基金
中国国家自然科学基金;
关键词
Digital circuits; fixed-point arithmetic; piecewise linear approximation; hardware; DIVISION;
D O I
10.5755/j01.eie.23.4.18717
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Inverse square root has played an important role in Cholesky decomposition, which devoted to hardware efficient compressed sensing. However, the performance is usually limited by the trade-off between throughput and precision. This paper presents hardware implementation of fixed-point single iterated multiplicative inverse square root. Multiple piecewise linear approximation in softly nonlinear range is used to compute the initial value. Single iterated Newton-Raphson method is employed to obtain high precision. Multiple constants multiplication technique is proposed to achieve high throughput. The combination of these techniques yields high performance in terms of throughput and precision. It obtains more than 70 % of throughput improvement and almost 100 x higher precision over the inverse square root Intellectual Property (IP) from Altera. In addition, Cholesky decomposition has been presented to validate the proposed architecture, which shows that 42 % of throughput improvement is achieved compared with the IP.
引用
收藏
页码:18 / 23
页数:6
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