Hardware Implementation of Single Iterated Multiplicative Inverse Square Root

被引:1
|
作者
Luo, Jun [1 ,2 ]
Huang, Qijun [2 ]
Luo, Hongwei [1 ]
Zhi, Yue [1 ]
Wang, Xiaoqiang [1 ]
机构
[1] China Elect Prod Reliabil & Environm Testing Res, 110 Dongguanzhuang Rd, Guangzhou, Guangdong, Peoples R China
[2] Wuhan Univ, Dept Phys & Technol, 16 Luojia Shan, Wuhan, Hubei, Peoples R China
基金
中国国家自然科学基金;
关键词
Digital circuits; fixed-point arithmetic; piecewise linear approximation; hardware; DIVISION;
D O I
10.5755/j01.eie.23.4.18717
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Inverse square root has played an important role in Cholesky decomposition, which devoted to hardware efficient compressed sensing. However, the performance is usually limited by the trade-off between throughput and precision. This paper presents hardware implementation of fixed-point single iterated multiplicative inverse square root. Multiple piecewise linear approximation in softly nonlinear range is used to compute the initial value. Single iterated Newton-Raphson method is employed to obtain high precision. Multiple constants multiplication technique is proposed to achieve high throughput. The combination of these techniques yields high performance in terms of throughput and precision. It obtains more than 70 % of throughput improvement and almost 100 x higher precision over the inverse square root Intellectual Property (IP) from Altera. In addition, Cholesky decomposition has been presented to validate the proposed architecture, which shows that 42 % of throughput improvement is achieved compared with the IP.
引用
收藏
页码:18 / 23
页数:6
相关论文
共 50 条
  • [21] Square Root and Inverse Square Root Computation Using a Fast FPGA Based Architecture
    Hasnat, Abul
    Dey, Atanu
    Halder, Santanu
    Bhattacharjee, Debotosh
    JOURNAL OF ACTIVE AND PASSIVE ELECTRONIC DEVICES, 2018, 13 (2-3): : 135 - 147
  • [22] THE GALOIS STRUCTURE OF THE SQUARE ROOT OF THE INVERSE DIFFERENT
    EREZ, B
    MATHEMATISCHE ZEITSCHRIFT, 1991, 208 (02) : 239 - 255
  • [23] A Modification of the Fast Inverse Square Root Algorithm
    Walczyk, Cezary J.
    Moroz, Leonid, V
    Cieslinski, Jan L.
    COMPUTATION, 2019, 7 (03)
  • [24] Fast enclosure for a matrix inverse square root
    Miyajima, Shinya
    LINEAR ALGEBRA AND ITS APPLICATIONS, 2015, 467 : 116 - 135
  • [25] EFFICIENT SQUARE ROOT IMPLEMENTATION ON THE 68000
    JOHNSON, KC
    ACM TRANSACTIONS ON MATHEMATICAL SOFTWARE, 1987, 13 (02): : 138 - 151
  • [26] Parallel algorithm for hardware implementation of inverse halftoning
    Siddiqi, UF
    Sait, SM
    Farooqui, AA
    2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS, 2005, : 2377 - 2380
  • [27] A novel approximation scheme for floating-point square root and inverse square root for FPGAs
    Pennestri, Pietro
    Huang, Yanqiu
    Alachiotis, Nikolaos
    2022 11TH INTERNATIONAL CONFERENCE ON MODERN CIRCUITS AND SYSTEMS TECHNOLOGIES (MOCAST), 2022,
  • [28] Reciprocation, square root, inverse square root, and some elementary functions using small multipliers
    Ercegovac, MD
    Lang, T
    Muller, JM
    Tisserand, A
    ADVANCED SIGNAL PROCESSING ALGORITHMS, ARCHITECTURES, AND IMPLEMENTATIONS VIII, 1998, 3461 : 543 - 554
  • [29] Reciprocation, square root, inverse square root, and some elementary functions using small multipliers
    Ercegovac, MD
    Lang, T
    Muller, JM
    Tisserand, A
    IEEE TRANSACTIONS ON COMPUTERS, 2000, 49 (07) : 628 - 637
  • [30] Single Clock Square Root Algorithm Based on Binomial Series and its FPGA Implementation
    Bagala, Tomas
    Fibich, Adam
    Hagara, Miroslav
    Kubinec, Peter
    Ondracek, Oldrich
    Stofanik, Vladimir
    Stojanovic, Radovan
    2018 7TH MEDITERRANEAN CONFERENCE ON EMBEDDED COMPUTING (MECO), 2018, : 141 - 144