Cross By Pass-Mesh Architecture for on-Chip Communication

Network-on-chip (NoC) is a new paradigm of System on chip (SoC). It has become a great focus of research by many groups during this era. Among all the on chip communication architectures that have been proposed until now, Mesh has proved to be the best architecture for implementation due to its simple and regular interconnection structure. In this paper, we present a new interconnect network architecture known as cross by pass mesh (CBP-Mesh) for on chip communication. The CBP-Mesh is much like traditional Mesh with the addition of two cross by pass links. By adding these cross by pass links, the number of hops in the networks and overall latency is reduced. The comparative analysis with other similar topologies like Mesh, Tours, 2DDgl-Mesh, SD-Mesh, X-Mesh and C2-Mesh, shows that the proposed topology outperforms in terms of latency. In the proposed architecture, the packets are routed towards their destinations in less time. These architectures are analyzed and compared in terms of topology characteristic, performance and cost of networks. Moreover results show that the proposed architecture perform better with respect to area utilization and power consumption.