A 200MHz 6-bit folding and interpolating ADC in 0.5-μm CMOS

被引：0

作者：

Jiang, XC ^{[1
]}

Wang, YT ^{[1
]}

Willson, AN ^{[1
]}

机构：

[1] Univ Calif Los Angeles, Integrated Circuits & Syst Lab, Dept Elect Engn, Los Angeles, CA 90095 USA

来源：

ISCAS '98 - PROCEEDINGS OF THE 1998 INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-6 | 1998年

关键词：

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

This paper presents the detailed design of a 200 MHz CMOS ADC with a folding and interpolating architecture. To overcome the input-frequency-multiplication problem inherent in such architectures, a front-end Sample/Hold circuit is used. The fully differential signal is folded by a factor of five and followed by a four-times interpolation. A double-averaging technique is explored and, with this technique, the analog folding stage can achieve approximately 12-bit linearity. To suppress the misalignment error, a bit alignment circuit is designed. The prototype chip includes about 1400 components and the active chip area is 0.4 mm(2). Its power consumption is approximately 150 mW at a 200 MHz sampling rate.

引用

页码：5 / 8

页数：4

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