A 200MHz 6-bit folding and interpolating ADC in 0.5-μm CMOS

This paper presents the detailed design of a 200 MHz CMOS ADC with a folding and interpolating architecture. To overcome the input-frequency-multiplication problem inherent in such architectures, a front-end Sample/Hold circuit is used. The fully differential signal is folded by a factor of five and followed by a four-times interpolation. A double-averaging technique is explored and, with this technique, the analog folding stage can achieve approximately 12-bit linearity. To suppress the misalignment error, a bit alignment circuit is designed. The prototype chip includes about 1400 components and the active chip area is 0.4 mm(2). Its power consumption is approximately 150 mW at a 200 MHz sampling rate.