Design of D-Band Transformer-Based Gain-Boosting Class-AB Power Amplifiers in Silicon Technologies

This paper presents design considerations and methodology for D-band transformer-based Class-AB gain-boosting power amplifiers (PAs) in three advanced silicon technologies: 28 nm bulk CMOS (complementary metal oxide semiconductor), 22 nm FD-SOI (fully-depleted silicon on insulator), and 130 nm SiGe BiCMOS (Silicon-germanium bipolar-CMOS). Firstly, the choice of processes and models together with de-embedding approaches are discussed and described. Then, a general design flow for a transformer-based matching network (TMN) is introduced to accelerate the design of multistage PAs. Further, two gain-boosting topologies are analyzed. The influence of capacitive gain-boosting on PA performance (maximum available power gain G(max), saturation power P-sat, drain efficiency DE and power-added efficiency PAE) is studied for different silicon technologies after properly sizing the PA transistors to reach an optimum load resistance R-opt. The inductive gain-boosting PA is explored and compared with the capacitive gain-boosting one in SiGe BiCMOS to achieve an even higher P-sat while maintaining a high G(max). Finally, A D-band 4-stage capacitive gain-boosting PA is fabricated in a 28 nm bulk CMOS process as a reference to verify the design methodology and simulation results, and its detailed design considerations are described. This prototyped D-band PA achieved the state-of-the-art results: a 22.5 dB Gp, 6.6 % PAE, 8 dBm Psat and 81.1 FoM with only 0.0265 mm(2) core area.