Extreme scaling with ultra-thin Si channel MOSFETs

被引：0

作者：

Doris, B ^{[1
]}

Ieong, M ^{[1
]}

Kanarsky, T ^{[1
]}

Zhang, Y ^{[1
]}

Roy, RA ^{[1
]}

Dokumaci, O ^{[1
]}

Ren, ZB ^{[1
]}

Jamin, FF ^{[1
]}

Shi, L ^{[1
]}

Natzle, W ^{[1
]}

Huang, HJ ^{[1
]}

Mezzapelle, J ^{[1
]}

Mocuta, T ^{[1
]}

Womack, S ^{[1
]}

Gribelyuk, M ^{[1
]}

Jones, TC ^{[1
]}

Miller, RJ ^{[1
]}

Wong, HSP ^{[1
]}

Haensch, W ^{[1
]}

机构：

[1] IBM Corp, SRDC, Microelect Div, Hopewell Jct, NY 12533 USA

来源：

INTERNATIONAL ELECTRON DEVICES 2002 MEETING, TECHNICAL DIGEST | 2002年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

We examine the scaling limits for planar single gate technology using the ultra-thin Si channel MOSFET. Characteristics for extreme scaled. devices with physical gate lengths down to 6nm and SOI channels as thin as 4nm are presented. For the first time, we report ring oscillators with 26nm gate lengths and ultra-thin Si channels.

引用

页码：267 / 270

页数：4

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