A clock circuit for high speed and high resolution pipeline ADC

被引：0
|
作者：
Zhang, Yong [1 ]
Li, Yaling [1 ]
Li, Ting [1 ]
机构：
[1] Sichuan Inst Solid State Circuits, Econ & Technol Dev Zone, 14 Huayuan Rd, Chongqing 400060, Peoples R China
来源：
2014 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC) | 2014年
关键词：
ADC; pipeline; jitter; duty cycle stabilizer;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A clock circuit for high speed and high resolution pipelined analog-to-digital conversion is presented. Double duty cycle stabilizers are proposed in the clock circuit, easing the first stage residue amplifier design; A new design method that minimizes the sampling clock jitter is applied in input clock preamplifier.
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收藏
页数：2
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