A passive filter for 10-Gb/s analog equalizer in 0.18-μm CMOS technology

被引：4

作者：

Lu, Jian-Hao ^{[1
]}

Luo, Chi-Lun ^{[1
]}

Liu, Shen-Iuan ^{[1
]}

机构：

[1] Natl Taiwan Univ, Grad Inst Elect Engn, Taipei 10617, Taiwan

来源：

2007 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE, PROCEEDINGS OF TECHNICAL PAPERS | 2007年

关键词：

D O I：

10.1109/ASSCC.2007.4425716

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, a high-speed and low-power analog equalizer for a 40-inch trace on FR4 board has been realized in 0.18-mu m CMOS technology. In order to achieve the low-power purpose and compensate the large signal attenuation of the FR4 trace simultaneously, the equalizer is presented by using the proposed RLC passive filter. This passive filter is used to obtain an additional peaking at high frequencies without consuming any power. In addition, the active filter using capacitive degeneration and active feedback techniques is also utilized to compensate the broadband loss. This circuit achieves a data rate of 10-Gb/s and consumes 34.2mW from a 1.8V supply with the output swing up to 200mV(p-p). The chip occupies 0.86x1.28mm(2) and the measured bit error rate (BER) is less than 10(-12).

引用

页码：404 / 407

页数：4

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