Barrier reliability of ALD TaN on sub-100 nm copper low-k interconnects

被引：0

作者：

Tokei, Z ^{[1
]}

Gailledrat, T ^{[1
]}

Li, YL ^{[1
]}

Schuhmacher, J ^{[1
]}

Mandrekar, T ^{[1
]}

Guggilla, S ^{[1
]}

Mebarki, B ^{[1
]}

Maex, K ^{[1
]}

机构：

[1] IMEC, B-3001 Heverlee, Belgium

来源：

ADVANCED METALLIZATION CONFERENCE 2004 (AMC 2004) | 2004年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

RC-delay performance and barrier reliability of an ALD TaN + PVD flash barrier was compared to PVD only barriers. The integration of an ALD TaN + PVD flash barrier results in lower leakage current than PVD schemes both at room temperature and at elevated temperature. Time Dependent Dielectric Breakdown experiments showed that an ALD + PVD flash barrier integrated with an SiOC:H low-k material leads to an interconnect lifetime above 10 years.

引用

页码：801 / 805

页数：5

共 50 条

[41] Suppressor Effects during Copper Superfilling of Sub-100 nm Lines
Huang, Q.
Baker-O'Neal, B. C.
Kelly, J. J.
Broekmann, P.
Wirth, A.
Emnet, C.
Martin, M.
Hahn, M.
Wagner, A.
Mayer, D.
ELECTROCHEMICAL AND SOLID STATE LETTERS, 2009, 12 (04) : D27 - D31
[42] Development of sub-10-nm atomic layer deposition barriers for Cu/low-k interconnects
Beyer, G
Satta, A
Schuhmacher, J
Maex, K
Besling, W
Kilpela, O
Sprey, H
Tempel, G
MICROELECTRONIC ENGINEERING, 2002, 64 (1-4) : 233 - 245
[43] Scaling effect on electromigration reliability for Cu/low-k interconnects
Pyun, JW
Lu, X
Yoon, S
Henis, N
Neuman, K
Pfeifer, K
Ho, PS
2005 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM PROCEEDINGS - 43RD ANNUAL, 2005, : 191 - 194
[44] Process Challenges for Integration of Copper Interconnects with Low-k Dielectrics
Gambino, J. P.
SILICON NITRIDE, SILICON DIOXIDE, AND EMERGING DIELECTRICS 11, 2011, 35 (04): : 687 - 699
[45] Characterization of sub-100 nm MOSFETs with high K gate dielectric
Zhu, Hui-Wen
Liu, Xiao-Yan
Shen, Chao
Kang, Jin-Feng
Han, Ru-Qi
Pan Tao Ti Hsueh Pao/Chinese Journal of Semiconductors, 2001, 22 (09): : 1107 - 1111
[46] BEOL process integration technology for 45nm node porous low-k/copper interconnects
Matsunaga, N
Nakamura, N
Higashi, K
Yamaguchi, H
Watanabe, T
Akiyama, K
Nakao, S
Fujita, K
Miyajima, H
Omoto, S
Sakata, A
Katata, T
Kagawa, Y
Kawashima, H
Enomoto, Y
Hasegawa, T
Shibata, H
PROCEEDINGS OF THE IEEE 2005 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE, 2005, : 6 - 8
[47] 248 nm photolithography compatibility on low-k dielectrics in BEOL interconnects
Hong, H
Xing, GQ
McKerrow, A
Kim, TS
Smith, PB
DESIGN, PROCESS INTEGRATION, AND CHARACTERIZATION FOR MICROELECTRONICS, 2002, 4692 : 547 - 554
[48] A low-damage ashing technique for improved reliability of 90-nm-node Cu/Low-k interconnects
Yatsuda, K
Saitoh, T
Tatsumi, T
Sato, T
Yoshida, M
Nogami, Y
Kawahara, K
Enomoto, Y
Yamane, T
Yamaguchi, Y
Morita, Y
Kadomura, S
ADVANCED METALLIZATION CONFERENCE 2003 (AMC 2003), 2004, : 687 - 692
[49] Study of CoTa alloy as barrier layer for Cu/low-k interconnects
Wang, Xu
Liu, Lin-Tao
He, Peng
Qu, Xin-Ping
Zhang, Jing
Wei, Shuhua
Mankelevich, Yuri A.
Baklanov, Mikhail R.
JOURNAL OF PHYSICS D-APPLIED PHYSICS, 2017, 50 (40)
[50] Integration of ALD TaN barriers in porous low-k interconnect for the 45 nm node and beyond; solution to relax electron scattering effect
Besling, WFA
Arnal, V
Guillaumond, JF
Guedj, C
Broekaart, M
Chapelon, LL
Farcy, A
Amaud, L
Torres, J
IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2004, TECHNICAL DIGEST, 2004, : 325 - 328

← 1 2 3 4 5 →