Hybrid Metallization with Cu in sub 30nm Interconnects

被引：4
|
作者：
van der Veen, Marleen H. [1 ]
Soethoudt, J. [1 ,2 ]
Delabie, A. [1 ,2 ]
Pedreira, O. Varela [1 ]
Gonzalez, V. Vega [1 ]
Lariviere, S. [1 ]
Teugels, L. [1 ]
Jourdan, N. [1 ]
Decoster, S. [1 ]
Struyf, H. [1 ]
Wilson, C. J. [1 ]
Croes, K. [1 ]
Tokei, Zs [1 ]
机构：
[1] IMEC, Kapeldreef 75, B-3001 Leuven, Belgium
[2] Univ Leuven, B-3001 Leuven, Belgium
来源：
2020 IEEE INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE (IITC) | 2020年
关键词：
ruthenium; prefill; hybrid; interconnects; resistance;
D O I：
10.1109/IITC47697.2020.9515643
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Patterns down to 21nm metal pitch (MP) have been used in the hybrid metallization scheme of Ru via prefill followed by a Cu trench metallization. The via resistance for Ru in hybrid with TaNRu/Cu trench fill is benchmarked to Co and Ru dual-damascene (DD) metallization schemes. At 30nm MP, a 40% via resistance reduction is observed upon introducing the Ru prefill prior to the Cu metallization. The Ru prefill significantly improved the via yield for the Cu metallization in 21nm MP. At this dimension, a 35% lower resistance is obtained with the Ru-Cu hybrid system when benchmarked to Co and Ru full fill with a lnm TiN barrier. The electromigration of the Ru-Cu hybrid system does not a show a performance degradation, making it a viable scaling scenario for DD metallizations in N5 technologies and beyond.
引用
收藏
页码：16 / 18
页数：3
相关论文
共 50 条
  • [1] RET and DFM Techniques for sub 30nm
    Yesilada, E.
    Entradas, J.
    Gardin, C.
    Pena, J. N.
    Villaret, A.
    Farys, V.
    Beylier, C.
    Robert, F.
    Postnikov, S.
    Armeanu, A. M.
    Moyroud, C.
    Chaoui, F.
    Granger, F. B.
    Toublan, O.
    OPTICAL MICROLITHOGRAPHY XXV, PTS 1AND 2, 2012, 8326
  • [2] Metallization of sub-30 nm interconnects: comparison of different liner/seed combinations
    Carbonell, Laureen
    Volders, Henny
    Heylen, Nancy
    Kellens, Kristof
    Caluwaerts, Rudy
    Devriendt, Katia
    Sanchez, Efrain Altamirano
    Wouters, Johan
    Gravey, Virginie
    Shah, Kavita
    Luo, Qian
    Sundarrajan, Arvind
    Lu, Jiang
    Aubuchon, Joseph
    Ma, Paul
    Narasimhan, Murali
    Cockburn, Andrew
    Tokei, Zsolt
    Beyer, Gerald P.
    PROCEEDINGS OF THE 2009 IEEE INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE, 2009, : 200 - +
  • [3] The Path Towards Sub 30nm Non Volatile Memories
    Shirota, R.
    Van Houdt, J.
    2009 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2009, : 87 - 87
  • [4] Advanced Elemental Analysis Methods for sub 30nm Defects in a Defect Review SEM
    Shemesh, Dror
    Boehm, Adi
    Greenberg, Ofir
    Dotan, Kfir
    2011 22ND ANNUAL IEEE/SEMI ADVANCED SEMICONDUCTOR MANUFACTURING CONFERENCE (ASMC), 2011,
  • [5] 30nm真空紫外光源
    激光与光电子学进展, 2008, (04) : 8 - 8
  • [6] Patterning Process Study for 30nm Hole
    Lee, Kilyoung
    Bok, Cheolkyu
    Kim, Jaeheon
    Lee, Byounghoon
    Bang, Jongsik
    Shim, Hyunkyung
    Kim, Sungjin
    Moon, James
    Yim, Donggyu
    Park, Sung-Ki
    ADVANCES IN RESIST MATERIALS AND PROCESSING TECHNOLOGY XXVIII, 2011, 7972
  • [7] Improvement of Poly Profile in Sub 30nm Device By Damage Engineering and Tilted Implantation Method
    Ham, Chul-Young
    Kwak, Noh-Yeal
    Lee, Sang-Soo
    Shin, Seung-Woo
    Ko, Min-Sung
    Kim, Jae-Mun
    Lee, Byung-Seok
    Kim, Jin-Woong
    Oh, Choong-Young
    Kim, Yong-Su
    Colombeau, Benjamin
    ION IMPLANTATION TECHNOLOGY 2010, 2010, 1321 : 41 - +
  • [8] CoWBP capping barrier layer for sub 90 nm Cu interconnects
    Almog, R. Ofek
    Sverdlov, Y.
    Goldfarb, I.
    Shacham-Diamand, Y.
    MICROELECTRONIC ENGINEERING, 2007, 84 (11) : 2450 - 2454
  • [9] Reliability Performance of Advanced Metallization Options for 30nm 1/2 pitch in SiCOH Low-k Materials
    Croes, K.
    Demuynck, S.
    Siew, Y. K.
    Wilson, C. J.
    Heylen, N.
    Beyer, G. P.
    Tokei, Zs.
    2011 IEEE INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE AND MATERIALS FOR ADVANCED METALLIZATION (IITC/MAM), 2011,
  • [10] Noble Design of Si-SOH in Trilayer Resist Process for Sub 30nm Logic Device
    Oh, Tae-Hwan
    Nam, Yunsuk
    Chang, Chansam
    Kim, Suhyun
    Kwak, Minkeun
    Kim, Dongsu
    Shin, Hongjae
    Lee, Nae-In
    Yoon, Jongshik
    ADVANCES IN RESIST MATERIALS AND PROCESSING TECHNOLOGY XXVII, PTS 1 AND 2, 2010, 7639
12345