Improvement of Poly Profile in Sub 30nm Device By Damage Engineering and Tilted Implantation Method

Conventionally, P-31 out-gassing of floating gate by succeeding thermal processes happens in NAND FLASH that use floating gate structure, and this P-31 out gassing causes degradation of PDR and cell characteristics in sub-30nm device. Usually, there is a method to keep PDR of in-situ doped poly-Si by increasing the concentration of P-31, but this method also causes cell characteristics degradation by trap charge of tunnel oxide. So, we used another method of ion implantation to control P-31 out-gassing concentration of floating gate by declining effective channel length. If we use methods of low energy and zero tilt implantation, P-31 Trap by dopant channeling occurs in tunnel oxide. So, we evaluated methods of low energy and tilted implantation. But in this case, there were poly loss and bending, due to the physical collision damage of implantation. Therefore, we evaluated the effects of tilt change, direction and temperature control of ion implantation to minimize poly loss of floating gate.