Self-aligned Ge nMOSFETs with gate-last process on GeOI platform

被引：0

作者：

Zhang, Yi ^{[1
]}

Han, Genquan ^{[1
]}

Liu, Yan ^{[1
]}

Liu, Huan ^{[1
]}

Li, Jing ^{[1
]}

Hao, Yue ^{[1
]}

机构：

[1] Xidian Univ, Sch Microelect, State Key Discipline Lab Wide Band Gap Semicond T, Xian 710071, Shaanxi, Peoples R China

来源：

2018 14TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT) | 2018年

基金：

中国国家自然科学基金;

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We report the self-aligned Ge nMOSFETs with gate-last process on GeOI platform. Dummy gate was adopted to define the channel part, and source/drain part can be heavily doped, enabling the full cover of heavily doped area. Cyclic oxidation was used to reduce the Ge channel surface roughness, and AFM results indicated that the RMS for the final sample was down to 0.33nm. I-on/I-off ratio of 2.5 orders at V-g of 0.5V was obtained for the fabricated nMOSFET device, with channel length of Slim and channel width of 2 mu m. Electron mobility versus reverse charge curve results indicated that the Coulomb scattering centers degraded the I-on, thus further performance can be enhanced by optimizing the channel passivation process.

引用

页码：219 / 221

页数：3

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